Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||||||||||||
1 |
and{cond4}Rd, Rx, Ry |
if ( cond4) Rd = Rx AND Ry; |
{d, x, y} ∈ {0, 1, …, 15} cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} |
Rev2+ |
|
Performs a bitwise logical AND between the specified registers and stores the result in the desti- nation register.
Q: |
Not affected. |
V: |
Not affected. |
N: |
Not affected. |
Z: |
Not affected. |
C: |
Not affected. |